Digital IP Developer profile
For our client we are looking for a Digital IP Developer profile Mandatory :
- Proficient with both RTL design in System Verilog and verification using UVM methodology
- Strong collaborative skills with System Architects and Integration teams
- Proficient in verification planning, reporting and driving verification closure. Must understand how a verification
project works, from start to finish
Experience with IP level and system level verificationStrong team playerExcellent communication skills, both written and oral EnglishExperience with UNIX and / or LinuxAt least 7 years in ASIC / FPGA industryStrong work ethics Meritorious :Experience with UART, SPI, I3C protocolsExperience with analog-mixed-signal type ASICsExperience using formal properties and tools, such as Jasper, OneSpin, InFact and similarExperience in using golden models / reference models in a test benchExperience in agile ways of working, agile scrumClearcase version control system experienceVHDL knowledgeC-programmingScripting in Perl, Python, Bash or C-shellMore than 10 years in the ASIC / FPGA industryAbility to travel to Kista, Stockholm once per every second month Start : ASAPDuration : 6-12 months
Location : Lund
Work load : Full-time Onsite
Working language : English and Swedish