ASIC / FPGA Design Engineer

Digital IP Developer profile

For our client we are looking for a Digital IP Developer profile Mandatory :

• Proficient with both RTL design in System Verilog and verification using UVM methodology
• Strong collaborative skills with System Architects and Integration teams
• Proficient in verification planning, reporting and driving verification closure. Must understand how a verificationproject works, from start to finish
• Experience with IP level and system level verification
• Strong team player
• Excellent communication skills, both written and oral English
• Experience with UNIX and / or Linux
• At least 7 years in ASIC / FPGA industry
• Strong work ethics Meritorious :
• Experience with UART, SPI, I3C protocols
• Experience with analog-mixed-signal type ASICs
• Experience using formal properties and tools, such as Jasper, OneSpin, InFact and similar
• Experience in using golden models / reference models in a test bench
• Experience in agile ways of working, agile scrum
• Clearcase version control system experience
• VHDL knowledge
• C-programming
• Scripting in Perl, Python, Bash or C-shell
• More than 10 years in the ASIC / FPGA industry
• Ability to travel to Kista, Stockholm once per every second month Start : ASAPDuration : 6-12 monthsLocation : LundWork load : Full-time OnsiteWorking language : English and Swedish