ASIC / FPGA Design Engineer

Digital IP Developer profile

For our client we are looking for a Digital IP Developer profile Mandatory :

• Proficient with both RTL design in System Verilog and verification using UVM methodology
• Strong collaborative skills with System Architects and Integration teams
• Proficient in verification planning, reporting and driving verification closure. Must understand how a verification

project works, from start to finish

Duration : 6-12 months

Location : Lund

Work load : Full-time Onsite

Working language : English and Swedish